zig-riscv-embedded

 1# From https://github.com/sifive/freedom-e-sdk/blob/c07ac84cbdd678963c4dc3ea34a68c47a8b53651/bsp/sifive-hifive1/openocd.cfg
 2#
 3# Copyright (c) 2019 SiFive, Inc.
 4# Licensed under Apache2 and MIT licenses.
 5
 6# JTAG adapter setup
 7adapter_khz     10000
 8
 9set chain_length 5
10
11interface ftdi
12ftdi_device_desc "Dual RS232-HS"
13ftdi_vid_pid 0x0403 0x6010
14
15ftdi_layout_init 0x0008 0x001b
16ftdi_layout_signal nSRST -oe 0x0020
17ftdi_layout_signal LED -data 0x0020
18
19set _CHIPNAME riscv
20jtag newtap $_CHIPNAME cpu -irlen $chain_length
21
22set _TARGETNAME_0 $_CHIPNAME.cpu
23
24target create $_TARGETNAME_0 riscv -chain-position $_TARGETNAME_0
25  
26$_TARGETNAME_0 configure -work-area-phys 0x80000000 -work-area-size 0x2710 -work-area-backup 1
27
28if { $chain_length == 6 } {
29  riscv use_bscan_tunnel 5
30}
31
32flash bank spi0 fespi 0x20000000 0 0 0 $_TARGETNAME_0 0x10014000
33
34init
35if { [info exists authkey] } {
36  riscv authdata_write $authkey
37}
38
39if {[ info exists pulse_srst]} {
40  ftdi_set_signal nSRST 0
41  ftdi_set_signal nSRST z
42  sleep 1500
43}
44halt
45
46flash protect 0 64 last off
47
48echo "Ready for Remote Connections"