zig-riscv-embedded - slow

 1// This is a hacky workaround for the fact that the HiFive1 FTDI chip
 2// doesn't do hardware flow control and the UART0 interrupt handler
 3// takes an eternity to complete since it does CoAP message handling.
 4package main
 5
 6import (
 7	"io"
 8	"time"
 9)
10
11const (
12	pause     = 1 * time.Second
13	fifoDepth = 8
14)
15
16type SlowWriter struct {
17	w io.Writer
18}
19
20func NewSlowWriter(w io.Writer) SlowWriter {
21	return SlowWriter{w: w}
22}
23
24func (w SlowWriter) Write(p []byte) (int, error) {
25	var n int
26	for i, c := range p {
27		if i != 0 && i%fifoDepth == 0 {
28			time.Sleep(pause)
29		}
30
31		written, err := w.w.Write([]byte{c})
32		if err != nil {
33			return n, err
34		}
35
36		n += written
37	}
38
39	return n, nil
40}