zig-riscv-embedded

 1// Based on https://github.com/agra-uni-bremen/riscv-vp/blob/f6e95b370cb6eab7024f1be26a2b8a8ae2c916be/sw/simple-sensor/bootstrap.S
 2//
 3// Copyright © 2017-2018, Group of Computer Architecture, University of Bremen
 4//
 5// Permission is hereby granted, free of charge, to any person obtaining a
 6// copy of this software and associated documentation files (the
 7// "Software"), to deal in the Software without restriction, including
 8// without limitation the rights to use, copy, modify, merge, publish,
 9// distribute, sublicense, and/or sell copies of the Software, and to
10// permit persons to whom the Software is furnished to do so, subject to
11// the following conditions:
12//
13// The above copyright notice and this permission notice shall be included
14// in all copies or substantial portions of the Software.
15//
16// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
17// OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
18// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
19// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
20// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
21// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
22// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
23
24.globl register_handler
25.globl lvl0_handler
26
27lvl0_handler:
28    # Store all register values on the stack
29    addi sp, sp, -4 * 32
30    sw x1, 0x0(sp)
31    sw x4, 3 * 4(sp)
32    sw x5, 4 * 4(sp)
33    sw x6, 5 * 4(sp)
34    sw x7, 6 * 4(sp)
35    sw x10, 9 * 4(sp)
36    sw x11, 10 * 4(sp)
37    sw x12, 11 * 4(sp)
38    sw x13, 12 * 4(sp)
39    sw x14, 13 * 4(sp)
40    sw x15, 14 * 4(sp)
41    sw x16, 15 * 4(sp)
42    sw x17, 16 * 4(sp)
43    sw x28, 27 * 4(sp)
44    sw x29, 28 * 4(sp)
45    sw x30, 29 * 4(sp)
46    sw x31, 30 * 4(sp)
47
48    # Jump to the level 1 trap handler written in Zig
49    jal level1IRQHandler
50
51    # Load all register values from the stack and return
52    lw x1, 0x0(sp)
53    lw x4, 3 * 4(sp)
54    lw x5, 4 * 4(sp)
55    lw x6, 5 * 4(sp)
56    lw x7, 6 * 4(sp)
57    lw x10, 9 * 4(sp)
58    lw x11, 10 * 4(sp)
59    lw x12, 11 * 4(sp)
60    lw x13, 12 * 4(sp)
61    lw x14, 13 * 4(sp)
62    lw x15, 14 * 4(sp)
63    lw x16, 15 * 4(sp)
64    lw x17, 16 * 4(sp)
65    lw x28, 27 * 4(sp)
66    lw x29, 28 * 4(sp)
67    lw x30, 29 * 4(sp)
68    lw x31, 30 * 4(sp)
69    addi sp, sp, 4 * 32
70    mret
71
72register_handler:
73    # Use lvl0_handler as the trap handler
74    la t0, lvl0_handler
75    csrw mtvec, t0
76
77    # Enable machine external interrupts (MIE bit)
78    li t1, 0x800
79    csrw mie, t1
80
81    # Globally enable machine mode interrupts (MIE bit)
82    li t1, 0x8
83    csrw mstatus, t1
84
85    # Return
86    ret