zig-riscv-embedded

Experimental Zig-based CoAP node for the HiFive1 RISC-V board

git clone https://git.8pit.net/zig-riscv-embedded.git

 1/*
 2 * Copyright (C) 2017 JP Bonn, Ken Rabold
 3 *
 4 * This file is subject to the terms and conditions of the GNU Lesser
 5 * General Public License v2.1. See the file LICENSE in the top level
 6 * directory for more details.
 7 */
 8
 9.section .init
10.globl _start
11.type _start,@function
12
13_start:
14    .cfi_startproc
15    .cfi_undefined ra
16.option push
17.option norelax
18    la gp, __global_pointer$
19.option pop
20    la sp, __StackTop
21
22
23    /* Load data section */
24    la a0, _data_lma
25    la a1, _data
26    la a2, _edata
27    bgeu a1, a2, 2f
281:
29    lw t0, (a0)
30    sw t0, (a1)
31    addi a0, a0, 4
32    addi a1, a1, 4
33    bltu a1, a2, 1b
342:
35
36    /* Clear bss section */
37    la a0, __bss_start
38    la a1, _end
39    bgeu a0, a1, 2f
401:
41    sw zero, (a0)
42    addi a0, a0, 4
43    bltu a0, a1, 1b
442:
45    call register_handler
46    call clock_init
47    call init
48
49    /* Loop forever */
501:
51    wfi
52    j 1b
53
54    .cfi_endproc